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Test of writing to the lower 4 bits of 64 words at 25MHz (also works at 50MHz but it's at the sampling limit of the USB scope).

12:52 a.m.

Test setup with one Digilent Analog Discovery 2.

6

Tim Edwards

Thanks to everyone who helped me get my SRAM chips tested! The COB boards work great (enough of them, anyway), the breakout board works great, and I was able to confirm read and write operation of all three of the 3.3V SRAM macros (256, 512, and 1024 byte) up to 50MHz. More extensive and exhaustive testing will be done, but getting a quick answer as to whether the 3.3V SRAMs are viable for the next tapeout was key.

Can we get some amount of reporting as to how good as a PUF that SRAM behaves? Like, reading the power-on bit pattern of a few dies and seeing how stable and unique it is per-die? If it's at least not-terrible, I could try next week about getting a probably-smallest-tested SRAM macro set up, if I can think of a way to read it at all without an electrical pad contact to the die.

@namibj : I don't have any kind of temperature force unit, so I won't be able to determine if the power-up pattern is stable over temperature. I would tend to expect it to be dependent on the 3.3V supply ramp, as well.

Tim Edwards

@namibj : I don't have any kind of temperature force unit, so I won't be able to determine if the power-up pattern is stable over temperature. I would tend to expect it to be dependent on the 3.3V supply ramp, as well.

temperature stability shouldn't matter tooo much; trying voltage corners of the nominal-3v3, or, if not difficult, operation at reduced voltage (e.g. the foundry Dualgate SCL is rated down to 1.62V) would be plenty sufficcient to get an idea of if it's looking to be usable or not. It doesn't have to be an exact match of the pattern, it just has to be closest-match by a physically-inspired metric (notably, I'd figure accounting for the impact of mismatch in the sense amplifiers would help the statistical-model-based matching, like perhaps using a polynomial chaos expansion surrogate model to decorrelate w.r.t. supply ramps and (as needed) temperature, and focus on die-specific mismatch instead. It'd be a next-week thing though, as this week I got the extended ttgf0p3 and have already pushed schedule from the next two days to the weekend.

namibj

Can we get some amount of reporting as to how good as a PUF that SRAM behaves? Like, reading the power-on bit pattern of a few dies and seeing how stable and unique it is per-die? If it's at least not-terrible, I could try next week about getting a probably-smallest-tested SRAM macro set up, if I can think of a way to read it at all without an electrical pad contact to the die.

I think what you will find is that some bit will always be the same at power-on but some will likely be more random. This means you'll need to transform this power-up pattern with random bits into a reproducible one.

Chips4Makers aka Staf Verhaegen

I think what you will find is that some bit will always be the same at power-on but some will likely be more random. This means you'll need to transform this power-up pattern with random bits into a reproducible one.

Well, I mostly care about it as being able to record them at the die sorter while the process still knows what reticle and what wafer any particular die came from (location within a reticle is obviously trivial to encode using mask ROM techniques), to then later post-packaging being able to read it out from in the circuit during e-testing and match it against the recorded database to recognize which of the dies it (with high likelihood) was, followed by printing the information onto a label or writing them into some type/choice of PROM, be it on-die or just on-PCB.